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ltc4269-1 1 42691fc ? ? ? ? 33m 39k 10f 30.9 1.21k 38.3k 100k 12k 10nf 10f 2.2f 0.1f 33pf 0.1f 2.2nf 1f t on sync pgdly uvlo pwrgd sense C v cmp sense + r cmp v neg shdn r class v portp v portn endly osc ltc4269-1 gnd fb v cc v in sg pg c cmp 10 h to micro controller ? 47f 0.18h 5v5a 100f + + 3.01k 27.4k t2p 14k 383k 54v from data pair 54v from spare pair +C ~~ +C ~~ 42691 ta01a typical application features applications description ieee 802.3at pd with synchronous no-opto flyback controller the ltc ? 4269-1 is an integrated powered device (pd) controller and switching regulator intended for high power ieee 802.3at and 802.3af applications. the ltc4269-1 is targeted for high ef? ciency, single and multioutput applications from 10w to 25w. by support- ing both 1-event and 2-event classi? cations, as de? ned by the ieee, the ltc4269-1 can be used in a wide range of product con? gurations. the ltc4269-1 synchronous, current mode, ? yback con- troller generates multiple supply rails in a single conversion step providing for the highest system ef? ciency while main- taining tight regulation across all outputs. the ltc4269-1 includes linear technologys patented no-opto feedback topology to provide full ieee 802.3 isolation without the need of an opto-isolator circuit. a true soft-start function allows graceful ramp-up of all output voltages. all linear technology pd solutions include a shutdown pin to provide ? exible auxiliary power options. the ltc4269-1 can accommodate adaptor voltages from 18v to 60v and supports both poe or aux dominance options. the ltc4269-1 is available in a space saving 32-pin dfn package. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5841643. n 25.5w ieee 802.3at compliant (type 2) pd n integrated state-of-the-art synchronous flyback controller C isolated power supply ef? ciency >92% C 88% ef? ciency including diode bridge and hot swap? fet n flexible integrated auxiliary power support n superior emi performance n robust 100v 0.7 (typ) integrated hot swap mosfet n ieee 802.3at high power available indicator n integrated signature resistor and programmable class current n undervoltage, overvoltage and thermal protection n short-circuit protection with auto-restart n programmable soft-start and switching frequency n complementary power good indicators n thermally enhanced 7mm 4mm dfn package n voip phones with advanced display options n dual-radio wireless access points n ptz security cameras n rfid readers n industrial controls 25w high ef? ciency pd solution downloaded from: http:///
ltc4269-1 2 42691fc pin configuration absolute maximum ratings pins with respect to v portn v portp voltage ......................................... C0.3v to 100v v neg voltage ......................................... C0.3v to v portp v neg pull-up current ..................................................1a shdn ....................................................... C0.3v to 100v r class , voltage ............................................ C0.3v to 7v r class source current ...........................................50ma pwrgd voltage (note 3) low impedance source ......v neg C0.3v to v neg +11v sink current .........................................................5ma pwrgd , t2p voltage ............................... C0.3v to 100v pwrgd , t2p sink current .....................................10ma pins with respect to gndv cc (note 3) low impedance source ....................... C0.3v to +18v sink current .......................................................30ma sense C , sense + voltage ........................ C0.5v to +0.5v uvlo, sync voltage ...................................C0.3v to v cc fb current ..............................................................2ma v cmp current .........................................................1ma operating ambient temperature range ltc4269c-1 ................................................. 0c to 70c ltc4269i-1 .............................................. C40c to 85c (notes 1, 2) 3231 30 29 28 27 26 25 24 23 22 21 20 19 18 17 33 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 v portp nc pwrgd pwrgd nc v neg v neg ncpg pgdly r cmp c cmp sense + sense C uvlov cmp shdn t2p r class nc v portn v portn ncnc sg v cc t on endly sync sfst osc fb top view dkd32 package 32-lead (7mm 4mm) plastic dfn t jmax = 125c, ja = 34c/w, jc = 2c/w gnd, exposed pad (pin 33) must be soldered to a heat sinking plane that is connected to v neg order information lead free finish tape and reel part marking* package description temperature range ltc4269cdkd-1#pbf ltc4269cdkd-1#trpbf 42691 32-lead (7mm 4mm) plastic dfn 0c to 70c ltc4269idkd-1#pbf ltc4269idkd-1#trpbf 42691 32-lead (7mm 4mm) plastic dfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc4269-1 3 42691fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. parameter conditions min typ max units interface controller (note 4) operating input voltage signature range classi? cation range on voltage off voltage overvoltage lockout at v portp (note 5) ll l l 1.5 12.530.0 71 60 9.8 21 37.2 vv v v v v on/off hysteresis window l 4.1 v signature/class hysteresis window l 1.4 v reset threshold state machine reset for 2-event classi? cation l 2.57 5.40 v supply current supply current at 57v measured at v portp pin l 1.35 ma class 0 current v portp = 17.5v, no r class resistor l 0.40 ma signature signature resistance 1.5v v portp 9.8v (note 6) l 23.25 26 k invalid signature resistance, shdn invoked 1.5v v portp 9.8v, v shdn = 3v (note 6) l 11 k invalid signature resistance during mark event (notes 6, 7) l 11 k classi? cation class accuracy 10ma < i class < 40ma, 12.5v < v portp < 21v (notes 8, 9) l 3.5 % classi? cation stability time v portp pin step to 17.5v, r class = 30.9, i class within 3.5% of ideal value (notes 8, 9) l 1m s normal operation inrush current v portp = 54v, v neg = 3v l 60 100 180 ma power fet on-resistance tested at 600ma into v neg , v portp = 54v l 0.7 1.0 power fet leakage current at v neg v portp = shdn = v neg = 57v l 1 a digital interface shdn input high level voltage l 3v shdn input low level voltage l 0.45 v shdn input resistance v portp = 9.8v, shdn = 9.65v l 100 k pwrgd , t2p output low voltage tested at 1ma, v portp = 54v. for t2p , must complete 2-event classi? cation to see active low l 0.15 v pwrgd , t2p leakage current pin voltage pulled 57v, v portp = v portn = 0v l 1 a pwrgd output low voltage tested at 0.5ma, v portp = 52v, v neg = 48v, output voltage is with respect to v neg l 0.4 v pwrgd clamp voltage tested at 2ma, v neg = 0v, voltage with respect to v neg l 12 16.5 v pwrgd leakage current v pwrgd = 11v, v neg = 0v, voltage with respect to v neg l 1 a downloaded from: http:///
ltc4269-1 4 42691fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. parameter conditions min typ max units pwm controller (note 10) power supply v cc turn-on voltage, v cc(on) l 14 15.3 16 v v cc turn-off voltage, v cc(off) 8 9.7 11 v v cc hysteresis v cc(on) C v cc(off) 4 5.6 6.5 v v cc shunt clamp v uvlo = 0v, i vcc = 15ma 19.5 20.5 v v cc supply current (i cc ) v cmp = open (note 11) 4 6.4 10 ma v cc start-up current v cc = 10v 180 400 a feedback ampli? er feedback regulation voltage (v fb ) 1.220 1.237 1.251 v feedback pin input bias current r cmp open 200 na feedback ampli? er transconductance i c = 10a 700 1000 1400 mho feedback ampli? er source or sink current 25 55 90 a feedback ampli? er clamp voltage v fb = 0.9v v fb = 1.4v 2.560.84 vv reference voltage line regulation 12v v cc 18v 0.005 0.02 %/ v feedback ampli? er voltage gain v cmp = 1.2v to 1.7v 1400 v/ v soft-start charging current v sfst = 1.5v 16 20 25 a soft-start discharge current v sfst = 1.5v, v uvlo = 0v 0.8 1.3 ma control pin threshold (v cmp ) duty cycle = min 1 v gate outputspg, sg output high level 6.6 7.4 8 v pg, sg output low level 0.01 0.05 v pg, sg output shutdown strength v uvlo = 0v; i pg , i sg = 20ma 1.6 2.3 v pg rise time c pg = 1nf 11 ns sg rise time c sg = 1nf 15 ns pg, sg fall time c pg , c sg = 1nf 10 ns current ampli? er switch current limit at maximum v cmp v sense + 88 98 110 mv v sense /v cmp 0.07 v/ v sense voltage overcurrent fault voltage v sense + , v sfst < 1v 206 230 mv timing switching frequency (f osc )c osc = 100pf 84 100 110 khz oscillator capacitor value (c osc ) (note 12) 33 200 pf minimum switch on time (t on(min) ) 200 ns flyback enable delay time (t endly ) 265 ns pg turn-on delay time (t pgdly ) 200 ns maximum switch duty cycle 85 88 % sync pin threshold 1.53 2.1 v sync pin input resistance 40 k downloaded from: http:///
ltc4269-1 5 42691fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: pins with 100v absolute maximum guaranteed for t 0c, otherwise 90v. note 3: active high pwrgd internal clamp self-regulates to 14v with respect to v neg . v cc has internal 19.5v clamp with respect to gnd. note 4: all voltages are with respect to v portn pin unless otherwise noted. note 5: input voltage speci? cations are de? ned with respect to ltc4269-1 pins and meet ieee 802.3af/at speci? cations when the input diode bridge is included. note 6: signature resistance is measured via the v/i method with the minimum v of 1v. the ltc4269-1 signature resistance accounts for the additional series resistance in the input diode bridge. note 7: an invalid signature after the 1st classi? cation event is mandated by the ieee802.3at standard. see the applications information section.note 8: class accuracy is with respect to the ideal current de? ned as 1.237/r class and does not include variations in r class resistance. note 9: this parameter is assured by design and wafer level testing. note 10: v cc = 14v; pg, sg open; v cmp = 1.5v, v sense C = 0v, r cmp = 1k, r ton = 90k, r pgdly = 27.4k, r endly = 90k, unless otherwise speci? ed. all voltages are with respect to gnd.note 11: supply current does not include gate charge current to the mosfets. see the applications information section. note 12: component value range guaranteed by design. electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. parameter conditions min typ max units load compensationload compensation to v sense offset voltage v rcmp with v sense + = 0v 1 mv feedback pin load compensation current v sense + = 20mv, v fb = 1.230v 20 a uvlo functionuvlo pin threshold (v uvlo ) 1.215 1.240 1.265 v uvlo pin bias current v uvlo = 1.2v v uvlo = 1.3v C0.25C4.50 0 C3.4 0.25 C2.50 aa downloaded from: http:///
ltc4269-1 6 42691fc typical performance characteristics input current vs input voltage 25k detection range input current vs input voltage input current vs input voltage v portp voltage (v) 0 0 v portp current (ma) 0.1 0.2 0.3 0.4 0.5 2 468 42691 g01 10 t a = 25c v portp voltage (v) (rising) 0 0 v portp current (ma) 10 20 30 40 50 10 20 30 40 42691 g02 50 60 t a = 25c class 4 class 3 class 2 class 1 class 0 v portp voltage (v) 12 9.5 v portp current (ma) 10.5 14 16 42691 g03 10.0 18 20 22 11.0 85c C40c class 1 operation signature resistance vs input voltage pwrgd , t2p output low voltage vs current active high pwrgd output low voltage vs current inrush current vs input voltage current (ma) 0 v pwrgd C v portn (v) v t2p C v portn (v) 0.4 0.6 8 42691 g07 0.2 0 2 4 6 10 0.8 t a = 25c current (ma) 0 0 pwrgd (v) 0.4 1.0 0.5 1 42691 g08 0.2 0.8 0.6 1.5 2 t a = 25c v portp C v neg = 4v v portp voltage (v) 40 85 current (ma) 115 45 50 42691 g09 55 60 90 100 105 110 95 90 100 105 110 95 class operation vs time on-resistance vs temperature v portp voltage (v) 1 22 v1:v2: signature resistance (k) 23 25 26 27 3 5 42691 g04 24 7 9 61 0 24 8 28 resistance = diodes: hd01 t a = 25c = $ v $ i v2 C v1 i 2 C i 1 ieee upper limit ieee lower limit ltc4269-1 only ltc4269-1 + 2 diodes v portp voltage 10v/div class current 10ma/div time (10s/div) 42691 g05 t a = 25c junction temperature (c) C50 0.2 resistance () 0.4 0.6 0.8 1.0 C25 02 55 0 42691 g06 75 100 downloaded from: http:///
ltc4269-1 7 42691fc temperature (c) C50 v cc (v) 15 25 42691 g10 1210 C25 0 50 98 1614 13 11 75 100 125 v cc(on) v cc(off) temperature (c) C50 i vcc (a) 200 250 300 25 75 42691 g11 150 100 C25 0 50 100 125 50 0 temperature (c) C50 8 9 25 75 42691 g12 76 C25 0 50 100 125 5 43 10 i vcc (ma) dynamic current c pg = 1nf, c sg = 1nf, f osc = 100khz static part current v cc = 14v temperature (c) C50 90 sense voltage (mv) 92 96 98 100 110104 0 50 75 42691 g13 94 106 108102 C25 25 100 125 fb = 1.1vsense = v sense + with v sense C = 0v temperature (c) C50 sense voltage (mv) 215 25 42691 g14 200190 C25 0 50 185180 220210 205 195 75 100 125 sense = v sense + with v sense C = 0v temperature (c) C50 90 f osc (khz) 92 96 98 100 110104 0 50 75 42691 g15 94 106 108102 C25 25 100 125 c osc = 100pf temperature (c) C50 1.230 v fb (v) 1.231 1.233 1.234 1.235 1.2401.237 0 50 75 42691 g16 1.232 1.238 1.2391.236 C25 25 100 125 temperature (c) C50 feedback pin input bias (na) 200 250 300 25 75 42691 g17 150 100 C25 0 50 100 125 50 0 r cmp open temperature (c) C50 v fb reset (v) 1.03 25 42691 g18 1.000.98 C25 0 50 0.970.96 1.041.02 1.01 0.99 75 100 125 typical performance characteristics v cc(on) and v cc(off) vs temperature v cc start-up current vs temperature v cc current vs temperature sense voltage vs temperature sense fault voltage vs temperature oscillator frequency vs temperature v fb vs temperature feedback pin input bias vs temperature v fb reset vs temperature downloaded from: http:///
ltc4269-1 8 42691fc v fb (v) 0.9 C70 i vcmp (a) C50 C30 C10 7030 1 1.1 1.4 50 10 1.2 1.3 1.5 42691 g19 125c 25c C40c temperature (c) C50 i vcmp (a) 60 65 70 25 75 42691 g20 55 50 C25 0 50 100 125 45 40 source current v fb = 1.1v sink current v fb = 1.4v temperature (c) C50 900 g m (mho) 950 1000 1050 1100 C25 0 25 50 42691 g21 75 100 125 temperature (c) C50 a v (v/v) 1550 25 42691 g22 14001300 C25 0 50 12501200 1150 1100 1600 1650 17001500 1450 1350 75 100 125 temperature (c) C50 uvlo (v) 1.240 1.245 1.250 25 75 42691 g23 1.235 1.230 C25 0 50 100 125 1.225 1.220 temperature (c) C50 3.4 3.5 3.7 25 75 42691 g24 3.33.2 C25 0 50 100 125 3.1 3.0 3.6 i uvlo (a) temperature (c) C50 sfst charge current (a) 23 25 42691 g25 2018 C25 0 50 1716 15 2221 19 75 100 125 capacitance (nf) 0 time (ns) 8070 60 50 40 30 20 10 0 8 42691 g26 246 1 0 7 135 9 t a = 25c fall time rise time temperature (c) C50 C25 19.0 v cc (v) 20.0 21.5 0 50 75 42691 g27 19.5 21.0 20.5 25 100 125 i cc = 10ma typical performance characteristics feedback ampli? er output current vs v fb feedback ampli? er source and sink current vs temperature feedback ampli? er g m vs temperature feedback ampli? er voltage gain vs temperature uvlo vs temperature i uvlo hysteresis vs temperature soft-start charge current vs temperature pg, sg rise and fall times vs load capacitance v cc clamp voltage vs temperature downloaded from: http:///
ltc4269-1 9 42691fc temperature (c) C50 t on(min) (ns) 330 25 42691 g28 300280 C25 0 50 270260 340320 310 290 75 100 125 r ton(min) = 158k temperature (c) C50 0 t pgdly (ns) 50 150 200 250 0 50 75 42691 g29 100 C25 25 100 125 300 r pgdly = 16.9k r pgdly = 27.4k temperature (c) C50 t endly (ns) 285 305 325 25 75 42691 g30 265 245 C25 0 50 100 125 225 205 r endly = 90k typical performance characteristics minimum pg on-time vs temperature pg delay time vs temperature enable delay time vs temperature pin functions shdn (pin 1): shutdown input. use this pin for auxiliary power application. drive shdn high to disable the pd interface operation and corrupt the signature resistance. if unused, tie shdn to v portn . t2p (pin 2): type 2 pse indicator, open-drain. low imped- ance indicates the presence of a type 2 pse. r class (pin 3): class select input. connect a resistor between r class and v portn to set the classi? cation load current (see table 2). nc (pins 4, 7, 8, 25, 28, 31): no connect. v portn (pins 5, 6): input voltage, negative rail. pin 5 and pin 6 must be electrically tied together at the package. sg (pin 9): synchronous gate drive output. this pin provides an output signal for a secondary-side synchro- nous recti? er. large dynamic currents may ? ow during voltage transitions. see the applications information section for details. v cc (pin 10): supply voltage pin. bypass this pin to gnd with a 4.7f, or more, capacitor. this pin has a 19.5v clamp to ground. v cc has an undervoltage lockout func- tion that turns the part on when v cc is approximately 15.3v and off at 9.7v. in a conventional trickle-charge bootstrapped con? guration, the v cc supply current increases signi? cantly during turn-on causing a benign relaxation oscillation action on the v cc pin if the part does not start normally. t on (pin 11): pin for external programming resistor to set the minimum time that the primary switch is on for each cycle. minimum turn-on facilitates the isolated feed- back method. see the applications information section for details. endly (pin 12): pin for external programming resistor to set enable delay time. the enable delay time disables the feedback ampli? er for a ? xed time after the turn-off of the primary-side mosfet. this allows the leakage inductance voltage spike to be ignored for ? yback voltage sensing. see the applications information section for details. sync (pin 13): external sync input. this pin is used to synchronize the internal oscillator with an external clock. the positive edge of the clock causes the oscillator to discharge causing pg to go low (off) and sg high (on). the sync threshold is typically 1.5v. tie to ground if unused. see the applications information section for details. sfst (pin 14): soft-start. this pin, in conjunction with a capacitor (c sfst ) to gnd, controls the ramp-up of peak primary current through the sense resistor. it is also used to control converter inrush at start-up. the sfst clamps downloaded from: http:///
ltc4269-1 10 42691fc the v cmp voltage and thus limits peak current until soft- start is complete. the ramp time is approximately 70ms per f of capacitance. leave sfst open if not using the soft-start function. osc (pin 15): oscillator. this pin, in conjunction with an external capacitor (c osc ) to gnd, de? nes the controller oscillator frequency. the frequency is approximately 100khz ? 100/c osc (pf). fb (pin 16): feedback ampli? er input. feedback is usually sensed via a third winding and enabled during the ? yback period. this pin also sinks additional current to compensate for load current variation as set by the r cmp pin. keep the thevenin equivalent resistance of the feedback divider at roughly 3k. v cmp (pin 17): frequency compensation control. v cmp is used for frequency compensation of the switcher con-trol loop. it is the output of the feedback ampli? er and the input to the current comparator. switcher frequency compensation components are placed on this pin to gnd. the voltage on this pin is proportional to the peak primary switch current. the feedback ampli? er output is enabled during the synchronous switch on time. uvlo (pin 18): undervoltage lockout. a resistive divider from v portp to this pin sets an undervoltage lockout based upon v portp level (not v cc ). when the uvlo pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from v cc . the v cc undervoltage lockout supersedes this function, so v cc must be great enough to start the part. the bias current on this pin has hysteresis such that the bias current is sourced when uvlo threshold is exceeded. this introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the upper divider resistor. the user can control the amount of hysteresis by adjusting the impedance of the divider. tie the uvlo pin to v cc if not using this function. see the applications information section for details. this pin is used for the uvlo function of the switching regulator. the pd interface section has an internal uvlo. sense C , sense + (pins 19, 20): current sense inputs. these pins are used to measure primary-side switch cur- rent through an external sense resistor. peak primary-side pin functions current is used in the converter control loop. make kelvin connections to the sense resistor r sense to reduce noise problems. sense C connects to the gnd side. at maximum current (v cmp at its maximum voltage) sense pins have 100mv threshold. the signal is blanked (ignored) during the minimum turn-on time. c cmp (pin 21): load compensation capacitive control. connect a capacitor from c cmp to gnd in order to reduce the effects of parasitic resistances in the feedback sensing path. a 0.1f ceramic capacitor suf? ces for most applica- tions. short this pin to gnd when load compensation is not needed. r cmp (pin 22): load compensation resistive control. connect a resistor from r cmp to gnd in order to com- pensate for parasitic resistances in the feedback sensing path. in less demanding applications, this resistor is not needed and this pin can be left open. see the applications information section for details. pgdly (pin 23): primary gate delay control. connect an external programming resistor (r pgdly ) to set delay from synchronous gate turn-off to primary gate turn-on. see the applications information section for details. pg (pin 24): primary gate drive. pg is the gate drive pin for the primary-side mosfet switch. large dynamic cur- rents ? ow during voltage transitions. see the applications information section for details. v neg (pins 26, 27): system negative rail. connects v neg to v portn through an internal power mosfet. pin 26 and pin 27 must be electrically tied together at the package. pwrgd (pin 29): power good output, open-collector. high impedence signals power-up completion. pwrgd is referenced to v neg and features a 14v clamp. pwrgd (pin 30): complementary power good output, open-drain. low impedance signals power-up completion. pwrgd is referenced to v portn . v portp (pin 32): positive power input. tie to the input port power through the input diode bridge.exposed pad (pin 33): ground. this is the negative rail connection for both signal ground and gate driver grounds of the ? yback controller. this pin should be connected to v neg . downloaded from: http:///
ltc4269-1 11 42691fc block diagram 19 sense C 20 sense + c cmp v cc 3v to fb pgate sgate currentsense amp r cmpf 50k load compensation C + C + C + C + C + C + C + 15.3v v cc uvlo uvlo i uvlo 18 osc 15 t on 11 pgdly 23 endly nc 12 sync 13 1.237v reference (v fb ) internal regulator uvlo 3v collapse detect error amp clamps 0.71.3 20v + C sr qq 1v 16 fb 17 v cmp 14 sfst tsd current trip slope compensation current comparator overcurrent fault logic block C + C + 21 r cmp gate drive 22 pg 24 sg 9 gnd (exposed pad) 33 oscillator set enable v cc gate drive bold line indicates high current path 14v 32 t2p 2 r class 3 nc 4 shdn pwrgd v portp 31 nc 1 30 pwrgd 29 25 nc 28 v neg v neg 26 control circuits classification current load 1.237v C + 16k 25k 7 v portn nc 8 nc 10 v cc 6 27 42691 bd v portn 5 downloaded from: http:///
ltc4269-1 12 42691fc applications information overview power over ethernet (poe) continues to gain popularity as more products are taking advantage of having dc power and high speed data available from a single rj45 connector. as poe continues to grow in the marketplace, powered device (pd) equipment vendors are running into the 13.0w power limit established by the ieee 802.3af standard. the iee802.3at standard establishes a higher power allocation for power over ethernet while maintaining backwards compatibility with the existing ieee 802.3af systems. power sourcing equipment (pse) and powered devices are distinguished as type 1 complying with the ieee 802.3af power levels, or type 2 complying with the ieee 802.3at power levels. the maximum available power of a type 2 pd is 25.5w. the ieee 802.3at standard also establishes a new method of acquiring power classi? cation from a pd and communi- cating the presence of a type 2 pse. a type 2 pse has the option of acquiring pd power classi? cation by performing 2-event classi? cation (layer 1) or by communicating with the pd over the data line (layer 2). in turn, a type 2 pd must be able to recognize both layers of communications and identify a type 2 pse. the ltc4269-1 is speci? cally designed to support the front end of a pd that must operate under the ieee 802.3at standard. in particular, the ltc4269-1 provides the t2p indicator bit which recognizes 2-event classi? cation. this indicator bit may be used to alert the ltc4269-1 output load that a type 2 pse is present. with an internal signature resistor, classi? cation circuitry, inrush control, and thermal shutdown, the ltc4269-1 is a complete pd interface solution capable of supporting in the next gen- eration pd applications. modes of operation the ltc4269-1 has several modes of operation depend- ing on the input voltage applied between the v portp and v portn pins. figure 1 presents an illustration of voltage and current waveforms the ltc4269-1 may encounter with the various modes of operation summarized in table 1. detection v1 classification on off off power bad off on t = r load c1 pwrgd tracks v portn detection v2 50 time 4030 v portp (v) 2010 5040 30 20 10 time v portp C v neg (v) C10 time C20C30 v portp C pwrgd (v) pwrgd C v neg (v) C40C50 2010 pd current inrush dv dt inrush c1 = power bad pwrgd tracks v portp pwrgd tracks v portp power bad power bad timetime power good power good detection i 1 classification detection i 2 load, i load 42691 f01 i class dependent on r class selection inrush = 100ma i 1 = v1 C 2 diode drops 25k i load = v portp r load i 2 = v2 C 2 diode drops 25k v portp pse i in r load r class c1 r class pwrgd pwrgd ltc4269-1 v neg v portn in detectionrange figure 1. v neg , pwrgd , pwrgd and pd current as a function of input voltage downloaded from: http:///
ltc4269-1 13 42691fc applications information table 1. ltc4269-1 modes of operation as a function of input voltage v portp Cv portn (v) ltc4269-1 modes of operation 0v to 1.4v inactive (reset after 1st classi? cation event) 1.5v to 9.8v (5.4v to 9.8v) 25k signature resistor detection before 1st classi? cation event (mark, 11k signature corrupt after 1st classi? cation event) 12.5v to on/off* classi? cation load current active on/off* to 60v inrush and power applied to pd load >71v overvoltage lockout, classi? cation and hot swap are disabled *on/off includes hysteresis. rising input threshold, 37.2v max. falling input threshold, 30v min. these modes satisfy the requirements de? ned in the ieee 802.3af/ieee 802.3at speci? cation. input diode bridge in the ieee 802.3af/ieee 802.3at standard, the modes of operation reference the input voltage at the pds rj45 connector. since the pd must handle power received in either polarity from either the data or the spare pair, input diode bridges br1 and br2 are connected between the rj45 connector and the ltc4269-1 (figure 2). the input diode bridge introduces a voltage drop that affects the range for each mode of operation. the ltc4269-1 compensates for these voltage drops so that a pd built with the ltc4269-1 meets the ieee 802.3af/ieee 802.3at-established voltage ranges. note the electrical characteristics are referenced with respect to the ltc4269- 1 package pins. detection during detection, the pse looks for a 25k signature resis- tor which identi? es the device as a pd. the pse will apply two voltages in the range of 2.8v to 10v and measures the corresponding currents. figure 1 shows the detection voltages v1 and v2 and the corresponding pd current. the pse calculates the signature resistance using the v/ i measurement technique. the ltc4269-1 presents its precision, temperature-com- pensated 25k resistor between the v portp and v portn pins, alerting the pse that a pd is present and requests power to be applied. the ltc4269-1 signature resistor also compensates for the additional series resistance introduced by the input diode bridge. thus a pd built with the ltc4269-1 conforms to the ieee 802.3af/ieee 802.3at speci? cations. rx C 6 rx + 3 tx C 2 tx + rj45 t1 powered device (pd) input 42691 f02 1 78 5 4 spare C spare + to phy br2 0.1f100v br1 d3 ltc4269-1 v portn v portp figure 2. pd front end using diode bridges on main and spare inputs downloaded from: http:///
ltc4269-1 14 42691fc applications information signature corrupt option in some designs that include an auxiliary power option, it is necessary to prevent a pd from being detected by a pse. the ltc4269-1 signature resistance can be corrupted with the shdn pin (figure 3). taking the shdn pin high will reduce the signature resistor below 11k which is an invalid signature per the ieee 802.3af/ieee 802.3at speci- ? cation, and alerts the pse not to apply power. invoking the shdn pin also ceases operation for classi? cation and disconnects the ltc4269-1 load from the pd input. if this feature is not used, connect shdn to v portn . table 2. summary of power classi? cations and ltc4269-1 r class resistor selection class usage maxi mum average power levels at input of pd (w) nominal classification load current (ma) ltc4269-1 r class resistor (, 1%) 0 type 1 0.44 to 13.0 < 0.4 open 1 type 1 0.44 to 3.84 10.5 124 2 type 1 3.84 to 6.49 18.5 69.8 3 type 1 6.49 to 13.0 28 45.3 4 type 2 13.0 to 25.5 40 30.9 2-event classification and the t2p pin a type 2 pse may declare the availability of high power by performing a 2-event classi? cation (layer 1) or by communicating over the high speed data line (layer 2). a type 2 pd must recognize both layers of communication. since layer 2 communication takes place directly between the pse and the ltc4269-1 load, the ltc4269-1 concerns itself only with recognizing 2-event classi? cation. in 2-event classi? cation, a type 2 pse probes for power classi? cation twice. figure 4 presents an example of a 2-event classi? cation. the 1st classi? cation event occurs when the pse presents an input voltage between 15.5v to 20.5v and the ltc4269-1 presents a class 4 load cur- rent. the pse then drops the input voltage into the mark voltage range of 7v to 10v, signaling the 1st mark event. the pd in the mark voltage range presents a load current between 0.25ma to 4ma. the pse repeats this sequence, signaling the 2nd clas- si? cation and 2nd mark event occurrence. this alerts the ltc4269-1 that a type 2 pse is present. the type 2 pse then applies power to the pd and the ltc4269-1 charges up the reservoir capacitor c1 with a controlled inrush cur- rent. when c1 is fully charged, and the ltc4269-1 declares power good, the t2p pin presents an active low signal, or low impedance output with respect to v portn . the t2p output becomes inactive when the ltc4269-1 input voltage falls below undervoltage lockout threshold. figure 3. 25k signature resistor with disable v portp v portn shdn ltc4269-1 signature disable 42691 f03 25k signatureresistor 16k to pse classification classi? cation provides a method for more ef? cient power allocation by allowing the pse to identify a pd power clas- si? cation. class 0 is included in the ieee speci? cation for pds that do not support classi? cation. class 1-3 partitions pds into three distinct power ranges. class 4 includes the new power range under ieee802.3at (see table 2). during classi? cation probing, the pse presents a ? xed voltage between 15.5v and 20.5v to the pd (figure 1). the ltc4269-1 asserts a load current representing the pd power classi? cation. the classi? cation load current is programmed with a resistor r class that is chosen from table 2. downloaded from: http:///
ltc4269-1 15 42691fc applications information detection v1 on off off off on t = r load c1 tracks v portn detection v2 time pd current 5040 30 v portp (v) 2010 40ma 5040 30 20 10 time v portp C v neg (v) C10 time C20C30 v portp C t2p (v) C40C50 dv dt inrush c1 = 42691 f04 inrush = 100ma r class = 30.9 i load = v portn r load v portp pse i in r load r class c1 r class t2p ltc4269-1 v neg v portn 1st class 1st mark 2nd mark detection v1 detection v2 1st mark 2nd mark 2nd class 1st class 2nd class load, i load inrush figure 4. v neg , t2p and pd current as a result of 2-event classi? cation signature corrupt during mark as a member of the ieee 802.3at working group, linear technology noted that it is possible for a type 2 pd to receive a false indication of a 2-event classi? cation if a pse port is pre-charged to a voltage above the detection voltage range before the ? rst detection cycle. the ieee working group modi? ed the standard to prevent this possibility by requiring a type 2 pd to corrupt the signature resistance during the mark event, alerting the pse not to apply power. the ltc4269-1 conforms to this standard by corrupting the signature resistance. this also discharges the port before the pse begins the next detection cycle. pd stability during classification classi? cation presents a challenging stability problem due to the wide range of possible classi? cation load current. the onset of the classi? cation load current introduces a voltage drop across the cable and increases the forward voltage of the input diode bridge. this may cause the pd to oscillate between detection and classi? cation with the onset and removal of the classi? cation load current. the ltc4269-1 prevents this oscillation by introducing a voltage hysteresis window between the detection and clas- si? cation ranges. the hysteresis window accommodates the voltage changes a pd encounters at the onset of the classi? cation load current, thus providing a trouble-free transition between detection and classi? cation modes. the ltc4269-1 also maintains a positive i-v slope through- out the classi? cation range up to the on-voltage. in the event a pse overshoots beyond the classi? cation voltage range, the available load current aids in returning the pd back into the classi? cation voltage range. (the pd input may otherwise be trapped by a reverse-biased diode bridge and the voltage held by the 0.1f capacitor). inrush current once the pse detects and optionally classi? es the pd, the pse then applies powers on the pd. when the ltc4269-1 input voltage rises above the on-voltage threshold, ltc4269-1 connects v neg to v portn through the internal power mosfet. downloaded from: http:///
ltc4269-1 16 42691fc applications information to control the power-on surge currents in the system, the ltc4269-1 provides a ? xed inrush current, allowing c1 to ramp up to the line voltage in a controlled manner. the ltc4269-1 keeps the pd inrush current below the pse current limit to provide a well controlled power-up characteristic that is independent of the pse behavior. this ensures a pd using the ltc4269-1 interoperability with any pse. turn-on/ turn-off threshold the ieee 802.3af/at speci? cation for the pd dictates a maximum turn-on voltage of 42v and a minimum turn-off voltage of 30v. this speci? cation provides an adequate voltage to begin pd operation, and to discontinue pd op- eration when the input voltage is too low. in addition, this speci? cation allows pd designs to incorporate an on/off hysteresis window to prevent start-up oscillations. the ltc4269-1 features an on/off hysteresis window (see figure 5) that conforms with the ieee 802.3af/at speci? ca- tion and accommodates the voltage drop in the cable and input diode bridge at the onset of the inrush current. once c1 is fully charged, the ltc4269-1 turns on is internal mosfet and passes power to the pd load. the ltc4269-1 continues to power the pd load as long as the input voltage figure 5. ltc4269-1 on/off and overvoltage lockout v portp c15f min v portn v neg ltc4269-1 42691 f05 to pse on/off and overvoltage lockout circuit pd load current-limitedturn on + v portp C v portn ltc4269-1 voltage power mosfet 0v to on* off >on* on ovlo off *includes on/off hysteresis on threshold 36.1v off threshold 30.7v ovlo threshold 71.0v figure 6. ltc4269-1 power good functional and state diagram 42691 f06 bold line indicates high current path pwrgd power not good inrush complete on < v portp < ovlo and not in thermal shutdown v portp < off v portp > ovlo or thermal shutdown power good 29 pwrgd ltc4269-1 30 v neg 27 v neg 26 v portn 6 v portn ovlo on/off tsd 5 control circuit does not fall below the off threshold. when the ltc4269-1 input voltage falls below the off threshold, the pd load is disconnected, and classi? cation mode resumes. c1 discharges through the ltc4269-1 circuitry. complementary power good when ltc4269-1 fully charges the load capacitor (c1), power good is declared and the ltc4269-1 load can safely begin operation. the ltc4269-1 provides complementary power good signals that remain active during normal op- eration and are de-asserted when the input voltage falls below the off threshold, when the input voltage exceeds the overvoltage lockout (ovlo) threshold, or in the event of a thermal shutdown (see figure 6). the pwrgd pin features an open collector output refer- enced to v neg which can interface directly with the uvlo pin. when power good is declared and active, the pwrgd pin is high impedance with respect to v neg . an internal 14v clamp limits the pwrgd pin voltage. connecting the pwrgd pin to the uvlo prevents the dc/dc converter downloaded from: http:///
ltc4269-1 17 42691fc from commencing operation before the pd interface completely charges the reservoir capacitor, c1. the active low pwrgd pin connects to an internal, open- drain mosfet referenced to v portn and may be used as an indicator bit when power good is declared and active. the pwrgd pin is low impedance with respect to v portn . pwrgd pin when shdn is invoked in pd applications where an auxiliary power supply invokes the shdn feature, the pwrgd pin becomes high imped- ance. this prevents the pwrgd pin that is connected to the uvlo pin from interfering with the dc/dc converter operations when powered by an auxiliary power supply. overvoltage lockout the ltc4269-1 includes an overvoltage lockout (ovlo) feature (figure 6) which protects the ltc4269-1 and its load from an overvoltage event. if the input voltage ex- ceeds the ovlo threshold, the ltc4269-1 discontinues pd operation. normal operations resume when the input voltage falls below the ovlo threshold and when c1 is charged up. thermal protection the ieee 802.3af/at speci? cation requires a pd to withstand any applied voltage from 0v to 57v inde? nitely. however, there are several possible scenarios where a pd may encounter excessive heating. during classi? cation, excessive heating may occur if the pse exceeds the 75ms probing time limit. at turn-on, when the load capacitor begins to charge, the instantaneous power dissipated by the pd interface can be large before it reaches the line voltage. and if the pd experiences a fast input positive voltage step in its operational mode (for example, from 37v to 57v), the instantaneous power dissipated by the pd interface can be large. the ltc4269-1 includes a thermal protection feature which protects the ltc4269-1 from excessive heating. if the ltc4269-1 junction temperature exceeds the over- temperature threshold, the ltc4269-1 discontinues pd operations and power good becomes inactive. normal operation resumes when the junction temperature falls below the overtemperature threshold and when c1 is charged up. external interface and component selection transformer nodes on an ethernet network commonly interface to the outside world via an isolation transformer. for pds, the isolation transformer must also include a center tap on the rj45 connector side (see figure 7). the increased current levels in a type 2 pd over a type 1 increase the current imbalance in the magnetics which can interfere with data transmission. in addition, proper termination is also required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. transformer vendors such as bel fuse, coilcraft, halo, pulse, and tyco (table 4) can assist in selecting an appropriate isolation transformer and proper termination methods. table 4. power over ethernet transformer vendors vendor contact information bel fuse inc. 206 van vorst street jersey city, nj 07302 tel: 201-432-0463 www.belfuse.com coilcraft inc. 1102 silver lake road gary, il 60013 tel: 847-639-6400 www.coilcraft.com halo electronics 1861 landings drive mountain view, ca 94043 tel: 650-903-3800 www.haloelectronics.com pca electronics 16799 schoenborn street north hills, ca 91343 tel: 818-892-0761 www.pca.com pulse engineering 12220 world trade drive san diego, ca 92128 tel: 858-674-8100 www.pulseeng.com tyco electronics 308 constitution drive menlo park, ca 94025-1164 tel: 800-227-7040 www.circuitprotection.com applications information downloaded from: http:///
ltc4269-1 18 42691fc input diode bridgefigure 2 shows how two diode bridges are typically con- nected in a pd application. one bridge is dedicated to the data pair while the other bridge is dedicated to the spare pair. the ltc4269-1 supports the use of either silicon or schottky input diode bridges. however, there are trade-offs in the choice of diode bridges. an input diode bridge must be rated above the maximum current the pd application will encounter at the tempera- ture the pd will operate. diode bridge vendors typically call out the operating current at room temperature, but derate the maximum current with increasing temperature. consult the diode bridge vendors for the operating current derating curve. a silicon diode bridge can consume over 4% of the available power in some pd applications. using schottky diodes can help reduce the power loss with a lower forward voltage. a schottky bridge may not be suitable for some high temperature pd application. the leakage current has a voltage dependency that can reduce the perceived signature resistance. in addition, the ieee 802.3af/at speci? cation mandates the leakage back-feeding through the unused bridge cannot generate more than 2.8v across a 100k resistor when a pd is powered with 57v. sharing input diode bridges at higher temperatures, a pd design may be forced to consider larger bridges in a bigger package because the maximum operating current for the input diode bridge is drastically derated. the larger package may not be accept- able in some space-limited environments. one solution to consider is to reconnect the diode bridges so that only one of the four diodes conducts current in each package. this con? guration extends the maximum operating current while maintaining a smaller package pro? le. figure 7 shows how to reconnect the two diode bridges. consult the diode bridge vendors for the derating curve when only one of four diodes is in operation. input capacitor the ieee 802.3af/at standard includes an impedance requirement in order to implement the ac disconnect function. a 0.1f capacitor (c14 in figure 7) is used to meet this ac impedance requirement. input series resistance linear technology has seen the customer community cable discharge requirements increase by nearly 500,000 times the original test levels. the pd must survive and operate applications information 1413 12 12 3 rx C 6 rx + 3 tx C 2 tx + rj45 t1 coilcraft ethi - 230ld 42691 f07 17 8 5 4 10 9 11 56 4 d3 smaj58a tvs br1hd01 10 br2hd01 to phy v portp ltc4269-1 c1 v portn v neg spare C spare + c140.1f 100v figure 7. pd front-end with isolation transformer, diode bridges, capacitors, and a transient voltage suppressor (tvs). downloaded from: http:///
ltc4269-1 19 42691fc reliably not only when an initially charged cable connects and dissipates the energy through the pd front end, but also when the electrical power system grounds are subject to very high energy events (e.g. lightning strikes). in these high energy events, adding 10 series resistance into the v portp pin greatly improves the robustness of the ltc4269-1 based pd. (see figure 7) the tvs limits the voltage across the port while the 10 and 0.1f ca- pacitance reduces the edge rate the lt4269-1 encounters across its pin. the added10 series resistance does not operationally affect the ltc4269-1 pd interface nor does it affect its compliance with the ieee802.3 standard. transient voltage suppressor the ltc4269-1 speci? es an absolute maximum voltage of 100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world can rou- tinely see excessive peak voltages. to protect the ltc4269- 1, install a transient voltage suppressor (d3) between the input diode bridge and the ltc4269-1 as shown in figure 7. a smaj58a is recommended for typical pd applications. however, a smbj58a may be preferred in applications where the pd front end must absorb higher energy dis- charge events. classi? cation resistor (r class ) the r class resistor sets the classi? cation load current, cor- responding to the pd power classi? cation. select the value of r class from table 2 and connect the resistor between the r class and v portn pins as shown in figure 4, or ? oat the r class pin if the classi? cation load current is not re- quired. the resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classi? cation circuit. load capacitor the ieee 802.3af/at speci? cation requires that the pd maintains a minimum load capacitance of 5f and does not specify a maximum load capacitor. however, if the load capacitor is too large, there may be a problem with inadvertent power shutdown by the pse. this occurs when the pse voltage drops quickly. the input diode bridge reverses bias, and the pd load momentarily powers off the load capacitor. if the pd does not draw power within the pses 300ms disconnection delay, the pse may remove power from the pd. thus, it is necessary to evaluate the load current and capacitance to ensure that an inadvertent shutdown cannot occur. the load capacitor can store signi? cant energy when fully charged. the pd design must ensure that this energy is not inadvertently dissipated in the ltc4269-1. for example, if the v portp pin shorts to v portn while the capacitor is charged, current will ? ow through the parasitic body diode of the internal mosfet and may cause permanent damage to the ltc4269-1. t2p interface when a 2-event classi? cation sequence successfully completes, the ltc4269-1 recognizes this sequence, and provides an indicator bit, declaring the presence of a type 2 pse. the open-drain output provides the option to use this signal to communicate to the ltc4269-1 load, or to leave the pin unconnected. figure 8 shows two interface options using the t2p pin and the opto-isolator. the t2p pin is active low and con- nects to an opto-isolator to communicate across the dc/ dc converter isolation barrier. the pull-up resistor r p is sized according to the requirements of the opto-isolator applications information 42691 f08 option 1: series configuration for active low/low impedance output C54v to pse r p to pd load v portp ltc4269-1 v portn t2p v + option 2: shunt configuration for active high/open collector output C54v to pse r p to pd load v portp ltc4269-1 v portn t2p v + figure 8. t2p interface examples downloaded from: http:///
ltc4269-1 20 42691fc operating current, the pull-down capability of the t2p pin, and the choice of v + . v + for example can come from the poe supply rail (which the ltc4269-1 v portp is tied to), or from the voltage source that supplies power to the dc/ dc converter. option 1 has the advantage of not drawing power unless t2p is declared active. shutdown interface to corrupt the signature resistance, the shdn pin can be driven high with respect to v portn . if unused, connect shdn directly to v portn . auxiliary power sourcein some applications, it is desirable to power the pd from an auxiliary power source such as a wall adapter. auxiliary power can be injected into an ltc4269-1-based pd at the input of the ltc4269-1 v portn , at v neg , or even the power supply output. in addition, some pd application may desire auxiliary supply dominance or may be con- ? gured for poe dominance. furthermore, pd applications may also opt for a seamless transition that is, without power disruption between poe and auxiliary power. the most common auxiliary power option injects power at v neg . figure 9 presents an example of this application. in this example, the auxiliary port injects 48v onto the line via diode d1. the components surrounding the shdn pin are selected so that the ltc4269-1 does not disconnect power to the output until the auxiliary supply exceeds 36v. this con? guration is an auxiliary-dominant con? guration. that is, the auxiliary power source supplies the power even if poe power is already present. this con? guration also provides a seamless transition from poe to auxiliary power when auxiliary power is applied, however, the removal of auxiliary power to poe power is not seamless. contact linear technology applications support for detail information on implementing a custom auxiliary power supply. ieee 802.3at system power-up requirement under the ieee 802.3at standard, a pd must operate under 13.0w as a type 1 pd until it recognizes a type 2 pse. initializing pd operation in 13.0w mode eliminates interoperability issue in case a type 2 pd connects to a type 1 pse. once the pd recognizes a type 2 pse, the ieee 802.3at standard requires the pd to wait 80ms in 13.0w operation before 25.5w operation can commence. maintain power signature in an ieee 802.3af/at system, the pse uses the maintain power signature (mps) to determine if a pd continues to require power. the mps requires the pd to periodically draw at least 10ma and also have an ac impedance less than 26.25k in parallel with 0.05f. if one of these conditions is not met, the pse may disconnect power to the pd. applications information figure 9. auxiliary power dominant pd interface example t1 42691 f09 tvs to phy 36v 100k 10k 10k d1 br1 +C br2 +C 0.1f100v c1 v portp ltc4269-1 v portn shdn v neg gnd +C isolated wall transformer rx C 6 rx + 3 tx C 2 tx + rj45 17 8 5 4 spare C spare + downloaded from: http:///
ltc4269-1 21 42691fc switching regulator overview the ltc4269-1 includes a current mode converter designed speci? cally for use in an isolated ? yback topology employing synchronous recti? cation. the ltc4269-1 operation is similar to traditional current mode switchers. the major difference is that output voltage feedback is derived via sensing the output voltage through the transformer. this precludes the need of an opto-isolator in isolated designs, thus greatly improving dynamic response and reliability. the ltc4269-1 has a unique feedback ampli? er that samples a transformer winding voltage during the ? yback period and uses that voltage to control output voltage. the internal blocks are similar to many current mode controllers. the differences lie in the feedback ampli? er and load compensation circuitry. the logic block also contains circuitry to control the special dynamic requirements of ? yback control. for more information on the basics of current mode switcher/controllers and isolated ? yback converters see application note 19. feedback ampli? erpseudo dc theory for the following discussion, refer to the simpli? ed switching regulator feedback ampli? er diagram (figure 10a). when the primary-side mosfet switch mp turns off, its drain voltage rises above the v portp rail. flyback occurs when the primary mosfet is off and the synchronous secondary mosfet is on. during ? yback the voltage on nondriven transformer pins is determined by the secondary voltage. the amplitude of this ? yback pulse, as seen on the third winding, is given as: v flbk = v out + i sec ?esr + r ds(on) () n sf r ds(on) = on-resistance of the synchronous mosfet ms i sec = transformer secondary current esr = impedance of secondary circuit capacitor, winding and traces n sf = transformer effective secondary-to-? yback winding turns ratio (i.e., n s /n flbk ) the ? yback voltage is scaled by an external resistive divider r1/r2 and presented at the fb pin. the feedback ampli? er compares the voltage to the internal bandgap reference. the feedback amp is actually a transconductance applications information ampli? er whose output is connected to v cmp only during a period in the ? yback time. an external capacitor on the v cmp pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. the regulation voltage at the fb pin is nearly equal to the bandgap reference v fb because of the high gain in the overall loop. the relationship between v flbk and v fb is expressed as: v flbk = r1 + r2 r2 ?v fb combining this with the previous v flbk expression yields an expression for v out in terms of the internal reference, programming resistors and secondary resistances: v out = r1 + r2 r2 ?v fb ?n sf ?? ? ?? ? i sec ?esr + r ds(on) () the effect of nonzero secondary output impedance is discussed in further detail (see load compensation theory). the practical aspects of applying this equation for v out are found in subsequent sections of the applications information. feedback ampli? er dynamic theory so far, this has been a pseudo-dc treatment of ? yback feedback ampli? er operation. but the ? yback signal is a pulse, not a dc level. provision is made to turn on the ? yback ampli? er only when the ? yback pulse is present, using the enable signal as shown in the timing diagram (figure 10b). minimum output switch on time (t on(min) ) the ltc4269-1 affects output voltage regulation via ? yback pulse action. if the output switch is not turned on, there is no ? yback pulse and output voltage information is not available. this causes irregular loop response and start-up/latchup problems. the solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. to accomplish this the current limit feedback is blanked each cycle for t on(min) . if the output load is less than that developed under these conditions, forced continuous operation normally occurs. see subsequent discussions in the applications information section for further details. downloaded from: http:///
ltc4269-1 22 42691fc applications information + C v fb 1.237v enable collapsedetect 1v ltc4269-1 feedback amp fb r1r2 16 17 v cmp v in primary flyback secondary ? ? ? mp t1 v flbk ms c vcmp 42691 f10a c out isolatedoutput + s r q C + primary-side mosfet drain voltage pg voltagesg voltage v in t on(min) enable delay min enable feedback amplifier enabled pg delay 42691 f10b v flbk 0.8 ? v flbk figure 10a. ltc4269-1 switching regulator feedback ampli? er figure 10b. ltc4269-1 switching regulator timing diagram downloaded from: http:///
ltc4269-1 23 42691fc enable delay time (endly) the ? yback pulse appears when the primary-side switch shuts off. however, it takes a ? nite time until the transformer primary-side voltage waveform represents the output voltage. this is partly due to rise time on the primary- side mosfet drain node, but, more importantly, is due to transformer leakage inductance. the latter causes a voltage spike on the primary side, not directly related to output voltage. some time is also required for internal settling of the feedback ampli? er circuitry. in order to maintain immunity to these phenomena, a ? xed delay is introduced between the switch turn-off command and the enabling of the feedback ampli? er. this is termed enable delay. in certain cases where the leakage spike is not suf? ciently settled by the end of the enable delay period, regulation error may result. see the subsequent sections for further details. collapse detect once the feedback ampli? er is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, which compares the ? yback voltage (fb) to a ? xed reference, nominally 80% of v fb . when the ? yback waveform drops below this level, the feedback ampli? er is disabled. minimum enable time the feedback ampli? er, once enabled, stays on for a ? xed minimum time period, termed minimum enable time. this prevents lockup, especially when the output voltage is abnormally low, e.g., during start-up. the minimum enable time period ensures that the v cmp node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. this time is set internally. effects of variable enable period the feedback ampli? er is enabled during only a portion of the cycle time. this can vary from the ? xed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. certain parameters of feedback amp behavior are directly affected by the variable enable period. these include effective transconductance and v cmp node slew rate. load compensation theory the ltc4269-1 uses the flyback pulse to obtain information about the isolated output voltage. an error source is caused by transformer secondary current ? ow through the synchronous mosfet r ds(on) and real life nonzero impedances of the transformer secondary and output capacitor. this was represented previously by the expression, i sec ? (esr + r ds(on) ). however, it is generally more useful to convert this expression to effective output impedance. because the secondary current only ? ows during the off portion of the duty cycle (dc), the effective output impedance equals the lumped secondary impedance divided by off time dc. since the off-time duty cycle is equal to 1 C dc, then: r s(out) = esr + r ds(on) 1 dc where: r s(out) = effective supply output impedance dc = duty cycle r ds(on) and esr are as de? ned previously this impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. in these cases, the external fb resistive divider is adjusted to compensate for nominal expected error. in more demanding applications, output impedance error is minimized by the use of the load compensation function. figure 11 shows the block diagram of the load compensation function. switch current is converted to a voltage by the external sense resistor, averaged and lowpass ? ltered by the internal 50k resistor r cmpf and the external capacitor on c cmp . this voltage is impressed across the external r cmp resistor by op amp a1 and transistor q3 producing a current at the collector of q3 that is subtracted from the fb node. this effectively increases the voltage required at the top of the r1/r2 feedback divider to achieve equilibrium. the average primary-side switch current increases to maintain output voltage regulation as output loading increases. the increase in average current increases r cmp resistor current which affects a corresponding increase applications information downloaded from: http:///
ltc4269-1 24 42691fc in sensed output voltage, compensating for the ir drops. assuming relatively ? xed power supply ef? ciency, eff, power balance gives: p out = eff ? p in v out ? i out = eff ? v in ? i in average primary-side current is expressed in terms of output current as follows: i in = k1?i out where: k1= v out v in ?eff so, the effective change in v out target is: v out = k1? r sense r cmp ?r1?n sf ? i out thus : v out i out = k1? r sense r cmp ?r1?n sf where:k1 = dimensionless variable related to v in , v out and ef- ? ciency, as previously explained r sense = external sense resistor nominal output impedance cancellation is obtained by equating this expression with r s(out) : k1? r sense r cmp ?r1?n sf = esr + r ds(on) 1 dc solving for r cmp gives: r cmp = k1? r sense ?1 dc () esr + r ds(on) ?r1?n sf the practical aspects of applying this equation to determine an appropriate value for the r cmp resistor are discussed subsequently in the applications information section. transformer design transformer design/speci? cation is the most critical part of a successful application of the ltc4269-1. the following sections provide basic information about designing the transformer and potential trade-offs. if you need help, the ltc applications group is available to assist in the choice and/or design of the transformer. turns ratios the design of the transformer starts with determining duty cycle (dc). dc impacts the current and voltage stress on the power switches, input and output capacitor rms currents and transformer utilization (size vs power). the ideal turns ratio is: n ideal = v out v in ? 1 dc dc avoid extreme duty cycles, as they generally increase cur- rent stresses. a reasonable target for duty cycle is 50% at nominal input voltage. for instance, if we wanted a 48v to 5v converter at 50% dc then: n ideal = 5 48 ? 1 0.5 0.5 = 1 9.6 in general, better performance is obtained with a lower turns ratio. a dc of 45.5% yields a 1:8 ratio. applications information ?? ? mp r cmpf 50k v in v flbk r2 load comp i r1 fb v fb q1 q2 r cmp c cmp r sense sense + 42691 f11 q3 C + a1 16 22 21 20 figure 11. load compensation diagram downloaded from: http:///
ltc4269-1 25 42691fc note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. when building a supply with multiple outputs derived through a multiple winding transformer, lower duty cycle can improve cross regulation by keeping the synchronous recti? er on longer, and thus, keep secondary windings coupled longer. for a multiple output transformer, the turns ratio between output windings is critical and affects the accuracy of the voltages. the ratio between two output voltages is set with the formula v out2 = v out1 ? n21 where n21 is the turns ratio between the two windings. also keep the secondary mosfet r ds(on) small to improve cross regulation. the feedback winding usually provides both the feedback voltage and power for the ltc4269-1. set the turns ratio between the output and feedback winding to provide a recti? ed voltage that under worst-case conditions is greater than the 11v maximum v cc turn-off voltage. n sf > v out 11 + v f where : v f = diode forward voltage for our example: n sf > 5 11 + 0.7 = 1 2.34 we will choose 1 3 leakage inductance transformer leakage inductance (on either the primary or secondary) causes a spike after the primary-side switch turn-off. this is increasingly prominent at higher load currents, where more stored energy is dissipated. higher ? yback voltage may break down the mosfet switch if it has too low a bv dss rating. one solution to reducing this spike is to use a clamp circuit to suppress the voltage excursion. however, suppressing the voltage extends the ? yback pulse width. if the ? yback pulse extends beyond the enable delay time, output voltage regulation is affected. the feedback system has a deliberately limited input range, roughly 50mv referred to the fb node. this rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. therefore, it is advisable to arrange the clamp circuit to clamp at as high a voltage as possible, observing mosfet breakdown, such that leakage spike duration is as short as possible. application note 19 provides a good reference on clamp design. as a rough guide, leakage inductance of several percent (of mutual inductance) or less may require a clamp, but exhibit little to no regulation error due to leakage spike behavior. inductances from several percent up to, perhaps, ten percent, cause increasing regulation error. avoid double digit percentage leakage inductances. there is a potential for abrupt loss of control at high load current. this curious condition potentially occurs when the leakage spike becomes such a large portion of the ? yback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real ? yback signal! it then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. this typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. once load current is reduced suf? ciently, the system snaps back to normal operation. when using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. operate the prototype supply at maximum expected load current. 2. temporarily short-circuit the output. 3. observe that normal operation is restored. if the output voltage is found to hang up at an abnormally low value, the system has a problem. this is usually evident by simultaneously viewing the primary-side mosfet drain voltage to observe ? rsthand the leakage spike behavior. applications information downloaded from: http:///
ltc4269-1 26 42691fc applications information a ? nal notethe susceptibility of the system to bistable behavior is somewhat a function of the load current/ voltage characteristics. a load with resistivei.e., i = v/r behavioris the most apt to be bistable. capacitive loads that exhibit i = v 2 /r behavior are less susceptible. secondary leakage inductance leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the ? yback pulse. this increases the output voltage target by a similar percentage. note that unlike leakage spike behavior, this phenomenon is independent of load. since the secondary leakage inductance is a constant percentage of mutual inductance (within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate. winding resistance effects primary or secondary winding resistance acts to reduce overall ef? ciency (p out /p in ). secondary winding resistance increases effective output impedance, degrading load regu-lation. load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. bi? lar winding a bi? lar, or similar winding, is a good way to minimize troublesome leakage inductances. bi? lar windings also improve coupling coef? cients, and thus improve cross regulation in multiple winding transformers. however, tight coupling usually increases primary-to-secondary capacitance and limits the primary-to-secondary breakdown voltage, so is not always practical. primary inductance the transformer primary inductance, l p , is selected based on the peak-to-peak ripple current ratio (x) in the transformer relative to its maximum value. as a general rule, keep x in the range of 20% to 40% (i.e., x = 0.2 to 0.4). higher values of ripple will increase conduction losses, while lower values will require larger cores. ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. l p is calculated from the following equation. l p = v in(max) ?dc min () 2 f osc ?x max ?p in = v in(max) ?dc min () 2 ?eff f osc ?x max ?p out where: f osc is the oscillator frequency dc min is the dc at maximum input voltage x max is ripple current ratio at maximum input voltage using common high power poe values, a 48v (41v < v in < 57v) to 5v/5.3a converter with 90% ef? ciency, p out = 26.5w and p in = 29.5w. using x = 0.4 n = 1/8 and f osc = 200khz: dc min = 1 1 + n?v in(max) v out = 1 1 + 1 8 ? 57 5 = 41.2% l p = 57v ? 0.412 () 2 200khz ? 0.4 ? 26.5w = 260h optimization might show that a more ef? cient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. a simple spreadsheet program is useful for looking at trade-offs. transformer core selection once l p is known, the type of transformer is selected. high ef? ciency converters use ferrite cores to minimize core loss. actual core loss is independent of core size for a ? xed inductance, but decreases as inductance increases. since increased inductance is accomplished through more turns of wire, copper losses increase. thus, transformer design balances core and copper losses. remember that increased winding resistance will degrade cross regulation and increase the amount of load compensation required. the main design goals for core selection are reducing copper losses and preventing saturation. ferrite core material saturates hard, rapidly reducing inductance when the peak design current is exceeded. this results downloaded from: http:///
ltc4269-1 27 42691fc applications information in an abrupt increase in inductor ripple current and, consequently, output voltage ripple. do not allow the core to saturate! the maximum peak primary current occurs at minimum v in : i pk = p in v in(min) ?dc max ?1 + x min 2 ?? ? ?? ? now : dc max = 1 1 + n?v in min () v out = 1 1 + 1 8 ? 41 5 = 49.4% x min = v in(min) ?dc max () 2 f osc ?l p ?p in = 41? 49.4% () 2 200khz ? 260h ? 29.5w = 0.267 using the example numbers leads to: i pk = 29.5w 41? 0.494 ?1 + 0.267 2 ?? ? ?? ? = 1.65a multiple outputs one advantage that the ? yback topology offers is that additional output voltages can be obtained simply by adding windings. designing a transformer for such a situation is beyond the scope of this document. for multiple windings, realize that the ? yback winding signal is a combination of activity on all the secondary windings. thus load regulation is affected by each windings load. take care to minimize cross regulation effects. setting feedback resistive divider the expression for v out developed in the operation section is rearranged to yield the following expression for the feedback resistors: r1 = r2 v out + i sec ?esr + r ds(on) () ?? ?? v fb ?n sf 1 ?? ?? ?? ?? continuing the example, if esr + r ds(on) = 8m , r2 = 3.32k, then: r1 = 3.32k 5 + 5.3 ? 0.008 1.237 ? 1/ 3 1 ?? ? ?? ? = 37.28k choose 37.4k.it is recommended that the thevenin impedance of the resistive divider (r1||r2) is roughly 3k for bias current cancellation and other reasons. current sense resistor considerations the external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. use a noninductive current sense resistor (no wire-wound resistors). mounting the resistor directly above an unbroken ground plane connected with wide and short traces keeps stray resistance and inductance low. the dual sense pins allow for a full kelvin connection. make sure that sense+ and senseC are isolated and connect close to the sense resistor. peak current occurs at 100mv of sense voltage v sense . so the nominal sense resistor is v sense /i pk . for example, a peak switch current of 10a requires a nominal sense resistor of 0.010 note that the instantaneous peak power in the sense resistor is 1w, and that it is rated accordingly. the use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability. size r sense using worst-case conditions, minimum l p , v sense and maximum v in . continuing the example, let us assume that our worst-case conditions yield an i pk of 40% above nominal, so i pk = 2.3a. if there is a 10% tolerance on r sense and minimum v sense = 88mv, then r sense ? 110% = 88mv/2.3a and nominal r sense = 35m . round to the nearest available lower value, 33m . downloaded from: http:///
ltc4269-1 28 42691fc applications information selecting the load compensation resistorthe expression for r cmp was derived in the operation section as: r cmp = k1? r sense ?1 dc () esr + r ds(on) ?r1?n sf continuing the example: k1= v out v in ?eff ?? ? ?? ? = 5 48 ? 90% = 0.116 dc= 1 1+ n?v in(nom) v out = 1 1 + 1 8 ? 48 5 = 45.5% if esr + r ds(on) = 8m r cmp = 0.116 ? 33m ?1 0.455 () 8m ? 37.4k ? 1 3 = 3.25k this value for r cmp is a good starting point, but empirical methods are required for producing the best results. this is because several of the required input variables are dif? cult to estimate precisely. for instance, the esr term above includes that of the transformer secondary, but its effective esr value depends on high frequency behavior, not simply dc winding resistance. similarly, k1 appears as a simple ratio of v in to v out times ef? ciency, but theoretically estimating ef? ciency is not a simple calculation. the suggested empirical method is as follows: 1. build a prototype of the desired supply including the actual secondary components. 2. temporarily ground the c cmp pin to disable the load compensation function. measure output voltage while sweeping output current over the expected range. approximate the voltage variation as a straight line. v out / i out = r s(out) . 3. calculate a value for the k1 constant based on v in , v out and the measured ef? ciency. 4. compute: r cmp = k1? r sense r s(out) ?r1?n sf 5. verify this result by connecting a resistor of this value from the r cmp pin to ground. 6. disconnect the ground short to c cmp and connect a 0.1f ? lter capacitor to ground. measure the output imped- ance r s(out) = v out / i out with the new compensation in place. r s(out) should have decreased signi? cantly. fine tuning is accomplished experimentally by slightly altering r cmp . a revised estimate for r cmp is: r cmp = r cmp ?1 + r s(out)cmp r s(out) ?? ?? ?? ?? where r ? cmp is the new value for the load compensation resistor. r s(out)cmp is the output impedance with r cmp in place and r s(out) is the output impedance with no load compensation (from step 2). setting frequency the switching frequency of the ltc4269-1 is set by an external capacitor connected between the osc pin and ground. recommended values are between 200pf and 33pf, yielding switching frequencies between 50khz and 250khz. figure 12 shows the nominal relationship between external capacitance and switching frequency. place the capacitor as close as possible to the ic and minimize osc c osc (pf) 30 50 f osc (khz) 100 200 300 100 200 42691 f12 figure 12. f osc vs osc capacitor values downloaded from: http:///
ltc4269-1 29 42691fc applications information trace length and area to minimize stray capacitance and potential noise pick-up. you can synchronize the oscillator frequency to an external frequency. this is done with a signal on the sync pin. set the ltc4269-1 frequency 10% slower than the desired external frequency using the osc pin capacitor, then use a pulse on the sync pin of amplitude greater than 2v and with the desired frequency. the rising edge of the sync signal initiates an osc capacitor discharge forcing primary mosfet off (pg voltage goes low). if the oscillator frequency is much different from the sync frequency, problems may occur with slope compensation and system stability. also, keep the sync pulse width greater than 500ns. selecting timing resistors there are three internal one-shot times that are programmed by external application resistors: minimum on-time, enable delay time and primary mosfet turn-on delay. these are all part of the isolated ? yback control technique, and their functions are previously outlined in the theory of operation section. the following information should help in selecting and/or optimizing these timing values. minimum output switch on-time (t on(min) ) minimum on-time is the programmable period during which current limit is blanked (ignored) after the turn-on of the primary-side switch. this improves regulator performance by eliminating false tripping on the leading edge spike in the switch, especially at light loads. this spike is due to both the gate/source charging current and the discharge of drain capacitance. the isolated ? yback sensing requires a pulse to sense the output. minimum on-time ensures that the output switch is always on a minimum time and that there is always a signal to close the loop. the ltc4269-1 does not employ cycle skipping at light loads. therefore, minimum on-time along with synchro- nous recti? cation sets the switch over to forced continuous mode operation. the t on(min) resistor is set with the following equation r ton(min) k () = t on(min) ns () 104 1.063 keep r ton(min) greater than 70k. a good starting value is 160k. enable delay time (endly) enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback ampli? er. as discussed earlier, this delay allows the feedback ampli? er to ignore the leakage inductance voltage spike on the primary side. the worst-case leakage spike pulse width is at maximum load conditions. so, set the enable delay time at these conditions. while the typical applications for this part use forced continuous operation, it is conceivable that a secondary- side controller might cause discontinuous operation at light loads. under such conditions, the amount of energy stored in the transformer is small. the ? yback waveform becomes lazy and some time elapses before it indicates the actual secondary output voltage. the enable delay time should be made long enough to ignore the irrelevant portion of the ? yback waveform at light loads. even though the ltc4269-1 has a robust gate drive, the gate transition time slows with very large mosfets. increase delay time as required when using such mosfets. the enable delay resistor is set with the following equation: r endly k () = t endly ns () 30 2.616 keep r endly greater than 40k. a good starting point is 56k. downloaded from: http:///
ltc4269-1 30 42691fc primary gate delay time (pgdly) primary gate delay is the programmable time from the turn-off of the synchronous mosfet to the turn-on of the primary-side mosfet. correct setting eliminates overlap between the primary-side switch and secondary-side syn- chronous switch(es) and the subsequent current spike in the transformer. this spike will cause additional component stress and a loss in regulator ef? ciency. the primary gate delay resistor is set with the following equation: r pgdly k () = t pgdly ns () + 47 9.01 a good starting point is 15k.soft-start function the ltc4269-1 contains an optional soft-start function that is enabled by connecting an external capacitor between the sfst pin and ground. internal circuitry prevents the control voltage at the v cmp pin from exceeding that on the sfst pin. there is an initial pull-up circuit to quickly bring the sfst voltage to approximately 0.8v. from there it charges to approximately 2.8v with a 20a current source. the sfst node is discharged to 0.8v when a fault occurs. a fault occurs when v cc is too low (undervoltage lockout), current sense voltage is greater than 200mv or the ics thermal (overtemperature) shutdown is tripped. when sfst discharges, the v cmp node voltage is also pulled low to below the minimum current voltage. once discharged and the fault removed, the sfst charges up again. in this manner, switch currents are reduced and the stresses in the converter are reduced during fault conditions. the time it takes to fully charge soft-start is: t ss = c sfst ?1.4v 20a = 70k ?c sfst f () switchers uvlo pin function the uvlo pin provides a user programming undervoltage lockout. this is typically used to provide undervoltage lockout based on v in . the gate drivers are disabled when uvlo is below the 1.24v uvlo threshold. an external resistive divider between the input supply and ground is used to set the turn-on voltage. the bias current on this pin depends on the pin volt- age and uvlo state. the change provides the user with adjustable uvlo hysteresis. when the pin rises above the uvlo threshold a small current is sourced out of the pin, increasing the voltage on the pin. as the pin voltage drops below this threshold, the current is stopped, further dropping the voltage on uvlo. in this manner, hysteresis is produced. referring to figure 13, the voltage hysteresis at v in is equal to the change in bias current times r a . the design procedure is to select the desired v in referred voltage hysteresis, v uvhys . then: r a = v uvhys i uvlo where: i uvlo = i uvlol C i uvloh is approximately 3.4a r b is then selected with the desired turn-on voltage: r b = r a v in(on) v uvlo C1 ?? ? ?? ? applications information v in r a ltc4269-1 (13a) uv turning on uvlo i uvlo r b v in r a ltc4269-1 (13b) uv turning off (13c) uv filtering uvlo uvlo r b v in r a2 r a1 c uvlo r b 42691 f13 i uvlo figure 13. uvlo pin function and recommended filtering downloaded from: http:///
ltc4269-1 31 42691fc applications information if we wanted a v in -referred trip point of 36v, with 1.8v (5%) of hysteresis (on at 36v, off at 34.2v): r a = 1.8v 3.4a = 529k, use 523k r b = 523k 36v 1.23v C1 ?? ? ?? ? = 18.5k, use 18.7k even with good board layout, board noise may cause problems with uvlo. you can ? lter the divider but keep large capacitance off the uvlo node because it will slow the hysteresis produced from the change in bias current. figure 13c shows an alternate method of ? ltering by split- ting the r a resistor with the capacitor. the split should put more of the resistance on the uvlo side.converter start-up the standard topology for the ltc4269-1 utilizes a third transformer winding on the primary side that provides both feedback information and local v cc power for the ltc4269-1 (see figure 14). this power bootstrapping improves converter ef? ciency but is not inherently self- starting. start-up is affected with an external trickle charge resistor and the ltc4269-1s internal v cc undervoltage lockout circuit. the v cc undervoltage lockout has wide hysteresis to facilitate start-up. in operation, the trickle charge resistor, r tr , is connected to v in and supplies a small current, typically on the order of 1ma to charge c tr . initially the ltc4269-1 is off and draws only its start-up current. when c tr reaches the v cc turn-on threshold voltage the ltc4269-1 turns on abruptly and draws its normal supply current. switching action commences and the converter begins to deliver power to the output. initially the output voltage is low and the ? yback voltage is also low, so c tr supplies most of the ltc4269-1 current (only a fraction comes from r tr .) v cc voltage continues to drop until, after some time (typically tens of milliseconds) the output voltage approaches its desired value. the ? yback winding then provides the ltc4269-1 supply current and the v cc voltage stabilizes. if c tr is undersized, v cc reaches the v cc turn-off threshold before stabilization and the ltc4269-1 turns off. the v cc node then begins to charge back up via r tr to the turn-on threshold, where the part again turns on. depending upon the circuit, this may result in either several on-off cycles before proper operation is reached, or permanent relaxation oscillation at the v cc node. r tr is selected to yield a worst-case minimum charging current greater than the maximum rated ltc4269-1 start-up current, and a worst-case maximum charging current less than the minimum rated ltc4269-1 supply current. r tr(max) < v in(min) v cc(on_max) i cc(st _max) and r tr(min) > v in(max) v cc(on_min) i cc(min) make c tr large enough to avoid the relaxation oscillatory behavior described above. this is complicated to deter- mine theoretically as it depends on the particulars of the secondary circuit and load behavior. empirical testing is recommended. note that the use of the optional soft-start function lengthens the power-up timing and requires a correspondingly larger value for c tr . + i vcc 42691 f14 r tr c tr v in v in i vcc v vcc v cc(on) threshold 0 v pg v cc ltc4269-1 pg gnd ? ? ? figure 14. typical power bootstrapping downloaded from: http:///
ltc4269-1 32 42691fc the ltc4269-1 has an internal clamp on v cc of approxi- mately 19.5v. this provides some protection for the part in the event that the switcher is off (uvlo low) and the v cc node is pulled high. if r tr is sized correctly, the part should never attain this clamp voltage.control loop compensation loop frequency compensation is performed by connect- ing a capacitor network from the output of the feedback ampli? er (v cmp pin) to ground as shown in figure 15. because of the sampling behavior of the feedback ampli? er, compensation is different from traditional current mode controllers. normally only c vcmp is required. r vcmp can be used to add a zero, but the phase margin improvement traditionally offered by this extra resistor is usually already accomplished by the nonzero secondary circuit impedance. c vcmp2 can be used to add an additional high frequency pole and is usually sized at 0.1 times c vcmp . slope compensation the ltc4269-1 incorporates current slope compensation. slope compensation is required to ensure current loop stability when the dc is greater than 50%. in some switching regulators, slope compensation reduces the maximum peak current at higher duty cycles. the ltc4269-1 eliminates this problem by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. minimum load considerations at light loads, the ltc4269-1 derived regulator goes into forced continuous conduction mode. the primary-side switch always turns on for a short time as set by the t on(min) resistor. if this produces more power than the load requires, power will ? ow back into the primary dur- ing the off period when the synchronization switch is on. this does not produce any inherently adverse problems, although light load ef? ciency is reduced. maximum load considerations the current mode control uses the v cmp node voltage and ampli? ed sense resistor voltage as inputs to the current comparator. when the ampli? ed sense voltage exceeds the v cmp node voltage, the primary-side switch is turned off. in normal use, the peak switch current increases while fb is below the internal reference. this continues until v cmp reaches its 2.56v clamp. at clamp, the primary-side mosfet will turn off at the rated 100mv v sense level. this repeats on the next cycle. it is possible for the peak primary switch currents as referred across r sense to exceed the max 100mv rating because of the minimum switch on time blanking. if the voltage on v sense exceeds 205mv after the minimum turn-on time, the sfst capacitor is discharged, causing the discharge of the v cmp capacitor. this then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. applications information 17 r vcmp v cmp c vcmp 42691 f15 c vcmp2 figure 15. v cmp compensation network in further contrast to traditional current mode switchers, v cmp pin ripple is generally not an issue with the ltc4269-1. the dynamic nature of the clamped feedback ampli? er forms an effective track/hold type response, whereby the v cmp voltage changes during the ? yback pulse, but is then held during the subsequent switch-on portion of the next cycle. this action naturally holds the v cmp voltage stable during the current comparator sense action (current mode switching). application note 19 provides a method for empirically tweaking frequency compensation. basically, it involves introducing a load current step and monitoring the response. downloaded from: http:///
ltc4269-1 33 42691fc short-circuit conditionsloss of current limit is possible under certain conditions such as an output short-circuit. if the duty cycle exhibited by the minimum on-time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. it ratchets up cycle-by-cycle to some higher level. expressed mathematically, the requirement to maintain short-circuit control is dc min = t on(min) ?f osc < i sc ?r sec + r ds(on) () v in ?n sp where: t on(min) is the primary-side switch minimum on-time i sc is the short-circuit output current n sp is the secondary-to-primary turns ratio (n sec /n pri ) (other variables as previously de? ned) trouble is typically encountered only in applications with a relatively high product of input voltage times secondary to primary turns ratio and/or a relatively long minimum switch on time. additionally, several real world effects such as transformer leakage inductance, ac winding losses and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. prudent design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction. output voltage error sources the ltc4269-1s feedback sensing introduces additional minor sources of errors. the following is a summary list: ? the internal bandgap voltage reference sets the reference voltage for the feedback ampli? er. the speci? cations detail its variation. ? the external feedback resistive divider ratio directly affects regulated voltage. use 1% components. ? leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio (ns/nf) from its ideal value. this increases the output voltage target by a similar percentage. since secondary leakage inductance is constant from part to part (within a tolerance) adjust the feedback resistor ratio to compensate. applications information ? the transformer secondary current ? ows through the impedances of the winding resistance, synchronous mosfet r ds(on) and output capacitor esr. the dc equivalent current for these errors is higher than the load current because conduction occurs only during the converters off-time. so, divide the load current by (1 C dc). if the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. otherwise, use the ltc4269-1 load compensation circuitry (see load compensation). if multiple output windings are used, the ? yback winding will have a signal that represents an amalgamation of all these windings impedances. take care that you examine worst-case loading conditions when tweaking the voltages. power mosfet selection the power mosfets are selected primarily on the criteria of on-resistance r ds(on) , input capacitance, drain-to-source breakdown voltage (bv dss ), maximum gate voltage (v gs ) and maximum drain current (id (max) ). for the primary-side power mosfet, the peak current is: i pk(pri) = p in v in(min) ?dc max ?1 + x min 2 ?? ? ?? ? where xmin is peak-to-peak current ratio as de? ned earlier. for each secondary-side power mosfet, the peak cur- rent is: i pk(sec) = i out 1 dc max ?1 + x min 2 ?? ? ?? ? select a primary-side power mosfet with a bvdss greater than: bv dss i pk l lkg c p + v in(max) + v out(max) n sp where nsp re? ects the turns ratio of that secondary-to primary winding. llkg is the primary-side leakage induc- tance and cp is the primary-side capacitance (mostly from the drain capacitance (coss) of the primary-side power mosfet). a clamp may be added to reduce the leakage inductance as discussed. downloaded from: http:///
ltc4269-1 34 42691fc applications information for each secondary-side power mosfet, the bv dss should be greater than: bv dss v out + v in(max) ? n sp choose the primary-side mosfet r ds(on) at the nominal gate drive voltage (7.5v). the secondary-side mosfet gate drive voltage depends on the gate drive method. primary-side power mosfet rms current is given by: i rms(pri) = p in v in(min) dc max for each secondary-side power mosfet rms current is given by: i rms(sec) = i out 1 dc max calculate mosfet power dissipation next. because the primary-side power mosfet operates at high v ds , a transition power loss term is included for accuracy. c miller is the most critical parameter in determining the transition loss, but is not directly speci? ed on the data sheets. c miller is calculated from the gate charge curve included on most mosfet data sheets (figure 16). with c miller determined, calculate the primary-side power mosfet power dissipation: p d(pri) = i rms(pri) 2 ? r ds(on) 1 + () + v in(max) ? p in(max) dc min ?r dr ? c miller v gate(max) v th ?f osc where: r dr is the gate driver resistance ( 10 ) v th is the mosfet gate threshold voltage f osc is the operating frequency v gate(max) = 7.5v for this part (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve. if you dont have a curve, use = 0.005/c ? t for low voltage mosfets. the secondary-side power mosfets typically operate at substantially lower v ds , so you can neglect transition losses. the dissipation is calculated using: p dis(sec) = i rms(sec) 2 ? r ds(on) (1 + ) with power dissipation known, the mosfets junction temperatures are obtained from the equation: t j = t a + p dis ? ja where t a is the ambient temperature and ja is the mosfet junction to ambient thermal resistance.once you have t j iterate your calculations recomputing and power dissipations until convergence. gate drive node considerationthe pg and sg gate drivers are strong drives to minimize gate drive rise and fall times. this improves ef? ciency, but the high frequency components of these signals can cause problems. keep the traces short and wide to reduce parasitic inductance. the parasitic inductance creates an lc tank with the mosfet gate capacitance. in less than ideal layouts, a series resistance of 5 or more may help to dampen the ringing at the expense of slightly slower rise and fall times and poorer ef? ciency. the ltc4269-1 gate drives will clamp the max gate voltage q a v gs ab 42691 f16 q b miller effect gate charge (q g ) figure 16. gate charge curve the ? at portion of the curve is the result of the miller (gate to-drain) capacitance as the drain voltage drops. the miller capacitance is computed as: c miller = q b q a v ds the curve is done for a given v ds . the miller capacitance for different v ds voltages are estimated by multiplying the computed c miller by the ratio of the application v ds to the curve speci? ed v ds . downloaded from: http:///
ltc4269-1 35 42691fc applications information to roughly 7.5v, so you can safely use mosfets with maximum v gs of 10v and larger. synchronous gate drivethere are several different ways to drive the synchronous gate mosfet. full converter isolation requires the synchro- nous gate drive to be isolated. this is usually accomplished by way of a pulse transformer. usually the pulse driver is used to drive a buffer on the secondary, as shown in the application on the front page of this data sheet. however, other schemes are possible. there are gate drivers and secondary-side synchronous controllers available that provide the buffer function as well as additional features. capacitor selection in a ? yback converter, the input and output current ? ows in pulses, placing severe demands on the input and output ? lter capacitors. the input and output ? lter capacitors are selected based on rms current ratings and ripple voltage. select an input capacitor with a ripple current rating greater than: i rms(pri) = p in v in(min) 1 dc max dc max continuing the example: i rms(pri) = 29.5w 41v 1 49.4% 49.4% = 0.728a keep input capacitor series resistance (esr) and inductance (esl) small, as they affect electromagnetic interference suppression. in some instances, high esr can also produce stability problems because ? yback converters exhibit a negative input resistance characteristic. refer to application note 19 for more information. the output capacitor is sized to handle the ripple current and to ensure acceptable output voltage ripple. the output capacitor should have an rms current rating greater than: i rms(sec) = i out dc max 1 dc max continuing the example: i rms(sec) = 5.3a 49.4% 1 49.4% = 5.24a this is calculated for each output in a multiple winding application. esr and esl along with bulk capacitance directly affect the output voltage ripple. the waveforms for a typical ? yback converter are illustrated in figure 17. the maximum acceptable ripple voltage (expressed as a percentage of the output voltage) is used to establish a starting point for the capacitor values. for the purpose of simplicity, we will choose 2% for the maximum output output voltage ripple waveform secondary current primary current i pri v cout 42691 f17 ringing due to esl i pri n v esr figure 17. typical flyback converter waveforms ripple, divided equally between the esr step and the charging/discharging v. this percentage ripple changes, depending on the requirements of the application. you can modify the following equations. for a 1% contribution to the total ripple voltage, the esr of the output capacitor is determined by: esr cout 1% ? v out ?1 dc max () i out downloaded from: http:///
ltc4269-1 36 42691fc the other 1% is due to the bulk c component, so use: c out i out 1% ? v out ?f osc in many applications, the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reliability and cost goals. for example, a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor satis? es the required bulk c. continuing our example, the output capacitor needs: esr cout 1% ? 5v ? 1 49.4% () 5.3a = 4m c out 5.3a 1%?5?200khz = 600f these electrical characteristics require paralleling several low esr capacitors possibly of mixed type. one way to reduce cost and improve output ripple is to use a simple lc ? lter. figure 18 shows an example of the ? lter. applications information optimization of output ripple must be done on a dedicated pc board. parasitic inductance due to poor layout can signi? cantly impact ripple. refer to the pc board layout section for more details. electro static discharge and surge protection the ltc4269-1 is speci? ed to operate with an absolute maximum voltage of C100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world (primarily v portn and v portp ) can routinely see peak voltages in excess of 10kv. to protect the ltc4269-1, it is highly recommended that the smaj58a unidirectional 58v transient voltage suppressor be installed between the diode bridge and the ltc4269-1 (d3 in figure 2). isolation the 802.3 standard requires ethernet ports to be electrically isolated from all other conductors that are user accessible. this includes the metal chassis, other connectors and any auxiliary power connection. for pds, there are two common methods to meet the isolation requirement. if there will be any user accessible connection to the pd, then an isolated dc/dc converter is necessary to meet the isolation requirements. if user connections can be avoided, then it is possible to meet the safety requirement by completely enclosing the pd in an insulated housing. in all pd applications, there should be no user accessible electrical connections to the ltc4269-1 or support circuitry other than the rj-45 port. layout considerations for the ltc4269-1 the ltc4269-1s pd front end is relatively immune to layout problems. excessive parasitic capacitance on the r class pin should be avoided. include a pcb heat sink to which the exposed pad on the bottom of the package can be soldered. this heat sink should be electrically connected to gnd. for optimum thermal performance, make the heat sink as large as possible. voltages in a pd can be as large as 57v for poe applications, so high voltage layout techniques should be employed. the shdn r load c out2 1f v out c out 470f c147f s 3 from secondary winding l1, 0.1h 42691 f18 + + figure 18. the design of the ? lter is beyond the scope of this data sheet. however, as a starting point, use these general guidelines. start with a c out 1/4 the size of the non? lter solution. make c1 1/4 of c out to make the second ? lter pole independent of c out . c1 may be best implemented with multiple ceramic capacitors. make l1 smaller than the output inductance of the transformer. in general, a 0.1h ? lter inductor is suf? cient. add a small ceramic capacitor (c out2 ) for high frequency noise on v out . for those interested in more details refer to second-stage lc filter design, ridley, switching power magazine, july 2000 p8-10. circuit simulation is a way to optimize output capacitance and ? lters, just make sure to include the component parasitic. ltc switchercad tm is a terri? c free circuit simulation tool that is available at www.linear.com. final switchercad is a trademark of linear technology corporation. downloaded from: http:///
ltc4269-1 37 42691fc pin should be separated from other high voltage pins, like v portp , v neg , to avoid the possibility of leakage currents shutting down the ltc4269-1. if not used, tie shdn to v portn . the load capacitor connected between v portp and v neg of the ltc4269-1 can store signi? cant energy when fully charged. the design of a pd must ensure that this energy is not inadvertently dissipated in the ltc4269-1. the polarity-protection diodes prevent an accidental short on the cable from causing damage. however if, v portn is shorted to v portp inside the pd while capacitor c1 is charged, current will ? ow through the parasitic body diode of the internal mosfet and may cause permanent damage to the ltc4269-1. in order to minimize switching noise and improve output load regulation, connect the gnd pin of the ltc4269-1 directly to the ground terminal of the v cc decoupling capacitor, the bottom terminal of the current sense resistor and the ground terminal of the input capacitor, using a ground plane with multiple vias. place the v cc capacitor immediately adjacent to the v cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. use a low esr ceramic capacitor. take care in pcb layout to keep the traces that conduct high switching currents short, wide and with minimal overall loop area. these are typically the traces associated with the switches. this reduces the parasitic inductance and also minimizes magnetic ? eld radiation. figure 19 outlines the critical paths. keep electric ? eld radiation low by minimizing the length and area of traces (keep stray capacitances low). the drain of the primary-side mosfet is the worst offender in this category. always use a ground plane under the switcher circuitry to prevent coupling between pcb planes. check that the maximum bv dss ratings of the mosfets are not exceeded due to inductive ringing. this is done by viewing the mosfet node voltages with an oscilloscope. if it is breaking down, either choose a higher voltage device, add a snubber or specify an avalanche-rated mosfet. place the small-signal components away from high frequen- cy switching nodes. this allows the use of a pseudo-kelvin connection for the signal ground, where high di/dt gate driver currents ? ow out of the ic ground pin in one direction (to the bottom plate of the v cc decoupling capacitor) and small-signal currents ? ow in the other direction. keep the trace from the feedback divider tap to the fb pin short to preclude inadvertent pick-up. for applications with multiple switching power converters connected to the same input supply, make sure that the input ? lter capacitor for the ltc4269-1 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple which could interfere with the ltc4269-1 operation. a few inches of pc trace or wire (l ? 100nh) between the c in of the ltc4269-1 and the actual source v in , is suf? cient to prevent current sharing problems. applications information t2 t1 c r c vin ms mp gate turn-on gate turn-on r sense ?? c vcc sg v cc pg v cc v cc v cc v in gate turn-off gate turn-off q4q3 c out 42691 f19 out ? ? ? + + + figure 19. layout critical high current paths downloaded from: http:///
ltc4269-1 38 42691fc typical applications 25w high ef? ciency triple output pd supply 100k 30.9 91 3.01k1% 29.4k1% 22f16v r920k 0.1f bas21 2.1k 150k 33pf 10f100v to isolated side via opto 0.1f 100v smaj58a 2.2f100v 0.1f t on 15k pgdly v neg s2b b1100 0.033 f sync r class shdn v cmp r cmp endly osc sfst ltc4269-1 gnd uvlo v portp v cc fb c cmp t2p 4.7h bss63lt + + v portn 107k 10 10k 10k 54v fromdata pair 54v from spare pair b1100 8 36v cmdz 5258b 330k1% 20k 1% 10k 680pf 3300pf 48vau in t t t t t 15m1% si4488dy si4362dy 10k 15 47 10 10 b0540w pa0184 bat54 330 2200pf 4700pf fmmt718 fmmt618 220pf 0.1f 1f 47f 2 100f 3.3v3a 0.33h pa1558nl 42691 ta02 sense C sense + sg pg 0.33h 1000pf 100v 100f t si4488dy 12v0.25a 22f 2 10 1500pf t si4470ey 47f 5v2a + +C + bas21 downloaded from: http:///
ltc4269-1 39 42691fc typical applications poe-based 5v, 5a power supply 100k 150 30.9 20 3.01k 27.4k 39k bas21 1.2k 38.3k 33pf 0.1f 100v 10f v portp 0.1f t on 12k pgdly v neg s1b b1100 s1b sync r class shdn v cmp r cmp endly osc ltc4269-1 gnd uvlo v portp v cc fb c cmp 10h bss63lt1 36vpdz36b smaj58a + v portn 107k 24k 10k 10 54v fromspare pair t1: pca electronics, epc3409g-lf or pulse, pa2369nl t2: pulse, pe-68386nl c1: pslb20j107m(45) 54v fromdata pair 48v auxiliarypower b1100 8 plcs 383k14.0k 10k 1nf 3.3nf t t t t 33m fds2582 10k 15 bat54 100 2.2nf mmbt3906 mmbt3904 t2 fds8880 1f t1 42691 ta03a sense C sense + sg pg pwrgd 0.18h c1100f 2.2nf 2kv t 47f 5v5a + + C 1f 22pf 1.5nf 10f + 2.2f 5.1 5.0 4.5 efficiency (%) 80 90 9276 8678 8874 72 84 82 output current (a) 42691 ta03b 42v port 57v port 0.5 1.0 2.0 3.0 1. 5 4. 0 2.5 3.5 50v port ef? ciency regulation output current (a) 0 efficiency (%) 4.95 5.20 5.25 1.0 2.0 3.0 4.85 5.104.90 5.154.80 4.75 5.05 5.00 0.5 1.5 4.0 5.0 2.5 3.5 4.5 42691 ta03c 42v port 57v port 50v port downloaded from: http:///
ltc4269-1 40 42691fc typical applications poe-based 12v, 2a power supply 100k 150 30.9 20 3.01k 29.4k 20k bas21 2.2k 38.3k 33pf 0.1f 100v 22f v portp 0.1f t on 12k pgdly v neg s1b s1b sync r class shdn v cmp r cmp endly osc ltc4269-1 gnd uvlo v portp v cc fb c cmp 10h bss63lt1 36vpdz36b smaj58a + v portn 107k 24k 10k 10 54v fromspare pair 54v fromdata pair 48v auxiliarypower b1100 8 plcs 383k14.0k 10k 1nf 4.7nf t t t t 33m fds2582 10k 15 bat54 b1100 100 2.2nf mmbt3906 mmbt3904 fds3572 1f 42691 ta04a sense C sense + sg pg 0.33h 2.2nf 2kv t 10f 12v2a + + C 1f 47pf 470pf 10f + 2.2f 15 t1: pca electronics, epc3410g-lf or pulse, pa2467nl t2: pulse, pe-68386nl c1: psldic476mh t2 t1 c147f pwrgd load current (a) 0.2 efficiency (%) 81 91 93 0.4 0.8 1.2 77 8779 8975 73 85 83 0.6 1.6 2.0 1.0 1.4 1.8 42691 ta04b 42v in 48v in 57v in load current (a) 0.2 11.9 12.4 12.5 0.38 0.74 1.1 11.7 12.211.8 12.311.6 11.5 12.1 12.0 0.56 1.5 2 0.92 1.3 1.6 1.8 42691 ta04c 42v in 57v in 50v in v out (v) ef? ciency regulation downloaded from: http:///
ltc4269-1 41 42691fc typical applications poe-based 3.3v, 7a power supply 100k 150 30.9 20 3.01k 29.4k 20k bas21 1k 38.3k 33pf 0.1f 100v 22f v portp 0.1f t on 12k pgdly v neg s1b s1b sync r class shdn v cmp r cmp endly osc ltc4269-1 gnd uvlo v portp v cc fb c cmp 10h bss63lt1 36vpdz36b smaj58a + v portn 107k 24k 10k 10 54v fromspare pair 54v fromdata pair 48v auxiliarypower b1100 8 plcs 383k14.0k 5.1k 2.2nf 6.8nf t t t t 33m fds2582 10k 15 bat54 100 2.2nf mmbt3906 mmbt3904 fds8670 1f 1f 16v 42691 ta05a sense C sense + sg pg 0.18h 2.2nf 2kv t 47f 3.3v7a + + C b1100 b0540w 1f 22pf 2.2nf 10f + 2.2f 5.1 47 t1: pca electronics, epc3408g-lf or pulse, pa2466nl t2: pulse, pe-68386nl c1: pslb20j107m(25) t2 t1 c1100f pwrgd ef? ciency regulation load current (a) 0.7 efficiency (%) 85 90 91 1.4 2.8 4.2 83 8884 8982 81 87 86 2.1 5.6 7.0 3.5 4.9 6.3 42691 ta05b 37v in 48v in 57v in load current (a) 3.27 3.42 3.453.21 3.363.24 3.393.18 3.15 3.33 3.30 42691 ta05c 42v in 50v in 57v in v out (v) 0.7 1.4 2.8 4.2 2.1 5.6 7.0 3.5 4.9 6.3 downloaded from: http:///
ltc4269-1 42 42691fc package description note: pin 1top mark (see note 6) bottom viewexposed pad r = 0.115typ 0.20 0.05 1 16 17 32 6.00 ref 6.43 0.10 2.65 0.10 4.00 0.10 0.75 0.05 0.00 C 0.05 0.200 ref 7.00 0.10 (dkd32) qfn 0707 rev a 0.40 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 = 45 chamfer 6.43 0.05 2.65 0.05 0.70 0.05 0.40 bsc 6.00 ref 3.10 0.05 4.50 0.05 0.40 0.10 0.20 0.05 packageoutline r = 0.05 typ dkd package 32-lead plastic dfn (7mm 4mm) (reference ltc dwg # 05-08-1734 rev a) downloaded from: http:///
ltc4269-1 43 42691fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 04/10 connected pwrgd pin to uvlo pin in typical application circuit drawings added text clarifying connecting pwrgd pin to uvlo pin in complementary power good section of the applications information section 1, 39-41 16, 17 c 08/12 updated maximum power levels for class 0 and class 3 to 13.0w added 10 resistor to v portp pin in figure 7 and supporting text in input series resistance section added smaj58a (tvs) recommendation paragraph figure 8: changed connection of photodiode (cathode side) from v neg to C54v rail figure 9: added schottky diode between v portn and v neg to make solution more robust to surges schematic changes to make solution more robust to surges: added 10 resistor to v portp pin, added schottky diode to v portn pin, and changed diode going from v portn to negative auxiliary input to s1b 14 18, 19 1919 20 38, 39, 40, 41 (revision history begins at rev b) downloaded from: http:///
ltc4269-1 44 42691fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0812 rev c printed in usa related parts part number description comments ltc4257-1 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classi? cation, dual current limit ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only, ieee-compliant pd detection and classi? cation, autonomous operation or i 2 c control ltc4259a-1 quad ieee 802.3af power over ethernet controller ac or dc disconnect, ieee-compliant pd detection and classi? cation, autonomous operation or i 2 c control ltc4263 single ieee 802.3af power over ethernet controller ac or dc disconnect, ieee-compliant pd detection and classi? cation, autonomous operation ltc4263-1 high power single pse controller internal switch, autonomous operation, 30w ltc4264 high power pd interface controller with 750ma current limit 750ma internal switch, programmable classi? cation current to 75ma. precision dual current limit with disable. ltc4265 ieee 802.3at high power pd interface controller with 2-event classi? cation 2-event classi? cation recognition, 100ma inrush current, single-class programming resistor, full compliance to 802.3at ltc4266 ieee 802.3at quad pse controller supports ieee 802.3at type 1 and type 2 pds, 0.34 channel resistance, advanced power management, high reliability 4-point pd detection, legacy capacitance detect ltc4266a quad ltpoe ++ pse controller provides up to 90w. backwards compatible with ieee 802.3af and ieee 802.3at pds. with programmable i cut /i lim , 2-event classi? cation, and port current and voltage monitoring ltc4266c quad ieee 802af pse controller with programmable i cut /i lim , 1-event classi? cation, and port current and voltage monitoring ltc4267-1 ieee 802.3af pd interface with an integrated switching regulator internal 100v 400ma switch, programmable class, 200khz constant frequency pwm ltc4267-3 ieee 802.3af pd interface with an integrated switching regulator 100v 400ma internal switch, programmable classi? cation, 300khz constant-frequency pwm, optimized for ieee-compliant pd system ltc4268-1 high power pd with synchronous no-opto flyback controller ieee 802.3af compliant, 750ma hot swap fet, 92% power supply ef? ciency, flexible aux support, superior emi ltc4269-2 ieee 802.3af/ieee 802.3at pd with synchronous forward controller 2-event classi? cation recognition, 94% power supply ef? ciency, flexible aux support, superior emi, 100khz to 500khz ltc4270/ltc4271 12-port poe/poe + /ltpoe ++ pse controller transformer isolation, supports type 1, type 2 and ltpoe ++ pds ltc4274 single ieee 802.3at poe pse controller with programmable i cut /i lim , 2-event classi? cation, and port current and voltage monitoring ltc4274a single ltpoe ++ pse controller provides up to 90w. backwards compatible with ieee 802.3af and ieee 802.3at pds. with programmable i cut /i lim , 2-event classi? cation, and port current and voltage monitoring ltc4274c single ieee 802.3af pse controller with programmable i cut /i lim , 1-event classi? cation, and port current and voltage monitoring ltc4278 ieee 802.3at pd interface with integrated flyback switching regulator 2-event classi? cation, programmable classi? cation, synchronous no-opto flyback controller, 50khz to 250khz, 12v auxillary support thinsot is a trademark of linear technology corporation. downloaded from: http:///

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